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A Precharged-Capacitor-Assisted Sensing (PCAS) scheme with novel level controller for low power DRAMs

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4 Author(s)
T. Kono ; Mitsubishi Electr. Corp., Hyogo, Japan ; T. Hamamoto ; K. Mitsui ; Y. Konishi

Summary form only given. Low power consumption of DRAMs is of great concern as handheld communication tools are widely used in various environments. The combination of Voltage-Down-Convertor (VDC) and Boosted Sense Ground (BSG) scheme meets the demand because it has advantages of: 1) reduction of voltage swing of bit-lines (BLs); 2) suppression of junction leakage current of memory cells because of needlessness of substrate bias; 3) decrease of subthreshold leakage current of memory cells because of negative gate-source voltage (Vgs) of an access transistor. It can lower the active current, extend the data retention time, and reduce the data retention current. The scheme, however, has some drawbacks. First, the smaller the voltage swing on BLs is, the slower the sense speed is. Second, BSG level (Vbsg) should be stable and tolerant of GND noise because the level difference between Vbsg and GND is small. This paper proposes a new scheme to solve these problems, called a Precharged-Capacitor-Assisted Sensing (PCAS) scheme. By adopting this scheme, proper voltage level on BLs can be generated stably with faster sense speed without losing the advantages of the conventional scheme.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999