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A 550-ps access, 900-MHz, 1-Mb ECL-CMOS SRAM

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11 Author(s)
Nambu, H. ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Kanetani, K. ; Yamasaki, K. ; Higeta, K.
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Summary form only given. An ultra-high-speed 1 Mb ECL-CMOS SRAM with 550 ps access time and 900 MHz operating frequency has been developed using 0.2 /spl mu/m BiCMOS technology. Three key techniques for achieving the high speed are a BiCMOS word driver with an NMOS level-shift circuit, a sense amplifier with a voltage-clamp circuit, and a BiCMOS write circuit with a variable impedance load of a bit line.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999

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