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A 1.0 ns access 770 MHz 36 Kb SRAM macro

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6 Author(s)
Uetake, T. ; Fujitsu Labs. Ltd., Kawasaki, Japan ; Maki, Y. ; Nakadai, T. ; Yoshida, K.
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Summary form only given. A 1.0 ns access, 770 MHz, 36 Kb SRAM macro using a 0.18 /spl mu/m CMOS low cost ASIC technology was developed. Key technologies used to achieve this high performance are full dynamic fast word driver circuits, noise free bit line load circuits and high speed dual-mode sense amplifier circuits. The word-bit size up to 2 Kword x 72 bit can be generated automatically by using a compiler.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999