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Gain cell block architecture for gigabit-scale chain ferroelectric RAM

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3 Author(s)
Takashima, D. ; Res. & Dev. Center, Toshiba Corp., Japan ; Oowaki, Y. ; Kunishima, I.

Summary form only given. A ferroelectric RAM (FRAM), especially a chain FRAM, has great potential for future high-density nonvolatile memory. However, two severe problems inherent to ferroelectric material make it difficult to realize gigabit scale FRAMs; cell polarization decreases drastically in scaled FRAMs, 1) because the cell polarization does not increase by thinning the ferroelectric film, and 2) because the three-dimensional ferroelectric capacitor is difficult to make. Therefore, a sufficient cell signal will not be obtained in 256 Mb FRAMs and beyond. The gain cell approach shown can be a solution for this problem because a large cell signal is obtained even with small cell polarization due to small load capacitance. However, a memory cell using a ferroelectric FET has drawbacks such as fabrication difficulty, poor data retention and read/write disturb. A memory cell composed of a gain transistor, a write transistor, a ferroelectric capacitor and a load capacitor, realizes stable read/write operation. However the memory cell size is very large. The concept of a new gain cell block is proposed. The gain cell block contains two chain cell blocks and a gain unit composed of a gain transistor and a write transistor. The gain unit is shared by the two chain cell blocks. This configuration realizes both a large readout cell signal and a small average cell size.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999