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A 1 V 6 b 50 MHz current-interpolating CMOS ADC

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4 Author(s)
Bang-Sup Song ; Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA ; Myung-Jun Choe ; P. Rakers ; S. Gillig

A current-interpolation technique is used to implement a 6 b 50 MHz ADC operable with a single battery cell as low as 0.9 V without charge pumping. The prototype chip, fabricated in a 0.35 /spl mu/m standard digital process, occupies an area of 2.4 mm/spl times/2 mm, and consumes 10 mW each in analog and digital supplies, respectively.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999