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GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link

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4 Author(s)
Ellersick, W. ; Comput. Syst. Lab., Stanford Univ., CA, USA ; Chih-Kong Ken Yang ; Horowitz, M. ; Dally, W.

A 4-bit 12-GSample/sec A/D converter (GAD) has been fabricated in a 0.25-/spl mu/m CMOS process to investigate the design of an equalized multi-level link. Clocked differential amplifiers were used to sample the input, followed by high-speed comparators with current-summed offset cancellation. Input bandwidth was measured at 2.5 GHz. Eight 1.5-GSample/sec flash A/D converters were interleaved to achieve the aggregate sample rate.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999