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A 3.6 Gb/s 340 mW 16:1 pipe-lined multiplexer using SOI-CMOS technology

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6 Author(s)
Nakura, T. ; Mitsubishi Electr. Corp., Hyogo, Japan ; Ueda, K. ; Kubo, K. ; Fernandez, W.
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This paper describes a 16:1 multiplexer (MUX) using a 0.18 /spl mu/m partially-depleted SOI-CMOS technology. Owing to a selector type architecture with a pipeline structure as well as small junction capacitances of SOI-CMOS devices, the MUX achieves 3.6 Gbps operation dissipating 340 mW at a power supply of 2.0 V.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999