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A 50 Gb/s 32/spl times/32 CMOS crossbar chip using asymmetric serial links

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4 Author(s)
Kun-Yung Ken Chang ; Comput. Syst. Lab., Stanford Univ., CA, USA ; Shang-Tse Chuang ; McKeown, N. ; Horowitz, M.

A 32/spl times/32 synchronous crossbar chip was designed in a 0.27 /spl mu/m CMOS technology for use in a high-speed network switch. The crossbar chip uses 32 Asymmetric Serial Links to achieve high speed at the interfaces and to reduce both power and area. The crossbar switch core is implemented with static CMOS multi-stage multiplexers with multicast capability. The chip operates successfully with links running at 1.6 Gb/s. The measured bit-error-rate is <10/sup -14/ when all channels and the switch core are operating. The crossbar chip consumes 5 W and provides a total bandwidth above 50 Gb/s.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999

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