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A compact 54/spl times/54-bit multiplier with improved Wallace-tree structure

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4 Author(s)
N. Itoh ; Syst. LSI Dev. Centre, Mitsubishi Electr. Corp., Hyogo, Japan ; Y. Naemura ; H. Makino ; Y. Nakase

As multimedia applications become popular, computers increasingly require high-speed floating point (FP) processing for three-dimension computer graphics (3DCG). Among various FP constructions, the FP multiplication is critical in both speed and area. The high-speed multiplier (MPY) frequently adopts the Wallace-tree method. However, this method requires complicated layout which increases the design cost and the chip area. We propose the new construction method of Wallace-tree which reduces the area with a simple layout. This paper describes a new method and its application to a 54/spl times/54-bit MPY design.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999