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Environmental effects in component packaging selection

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3 Author(s)
Siddhaye, S. ; California Univ., Berkeley, CA, USA ; Sheng, P. ; Ooi, C.

Design for environment activities in electronics have been focused on issues of product life-cycle at the board design level and to facility-level process and material choices at the semiconductor fabrication level. An important bridge between these two domains has been the influence of component selection, particularly packaging selection, on environmental impacts. Component packaging influences waste generation in two respects. First, packaging type (i.e. DIP, QFP, BGA, etc.) and size dictates direct production waste in stamping, molding and plating operations. The waste streams from these operations include copper, polymerized thermoset plastic, caustic and acidic effluents and also small traces of silver epoxy. Since many waste components are nonrecyclable and/or have high hazardous content, effective management of direct waste emissions is a critical design task. Second, packaging selection indirectly affects waste generation at the printed circuit board (PCB) level through layout and board sizing decisions. The waste streams from board fabrication include composite scrap (usually glass epoxy), metals (copper foil and dissolved solutions) and catalyst wastes (aqueous photoresist, developer and stripper solutions and hole drilling scrap and tooling). The analysis approach undertaken in this study relies on the development of a toolset of unit process models for packaging manufacturing which develops relationships between package parameters, process parameters and waste outputs. By linking a chain of process models, a mathematical description of a packaging production sequence can be estimated. The models are formulated using the line data collected on plastic quad flat package (PQFP) lines. From the process models, a case comparison of the environmental impacts for two alternative packages for components is developed. Two designs, a design that employs almost all small outline integrated circuits (SOICs) and dual in-line packages (DIPs) (except where lead count necessitates PQFPs) vs. the same design that employs all PQFPs are considered. A case study illustrating the corresponding PCB level impacts due to component packaging selection is also presented. The bare board chosen in both cases is a standard FR4 board

Published in:

Electronics Packaging Manufacturing, IEEE Transactions on  (Volume:22 ,  Issue: 3 )

Date of Publication:

Jul 1999

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