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Design of ADPLL for both large lock-in range and good tracking performance

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2 Author(s)
Nam-Guk Kim ; Dept. of Electr. Eng., Seoul Nat. Univ., South Korea ; In-Joong Ha

This paper describes a new all-digital phase locked loop (ADPLL). The proposed ADPLL contains a frequency offset estimator and a phase-error estimator. Thereby, it can provide both large lock-in range and good tracking performance. Furthermore, it does not suffer severely from the phase jitter due to the quantization effect of the numerically controlled oscillator. In addition to some mathematical performance analysis, various simulation and experimental results are also presented to illuminate further the practical use and the excellent performance of the proposed ADPLL

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IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing  (Volume:46 ,  Issue: 9 )