Referenced Items are not available for this document.
The channel length of the DRAM transfer gate device continues to shrink aggressively. Conventional scaling techniques are limited in their applicability for the low leakage DRAM transfer device. There is thus a need for novel integration schemes that allow the continued cell shrinkage with only limited shrinking of the channel length. In this paper, we present an integration scheme which allows for a larger gate polysilicon length for a given pitch thus improving array device leakage (by about one generation) for a given technology
Published in:
VLSI Technology, Systems, and Applications, 1999. International Symposium on
Date of Conference: 1999
- Page(s):
- 255 - 257
- Meeting Date :
- 08 Jun 1999-10 Jun 1999
- Print ISBN:
- 0-7803-5620-9
- INSPEC Accession Number:
- 6504381
- Conference Location :
- Taipei
- Digital Object Identifier :
- 10.1109/VTSA.1999.786048
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