A 3-D stacked chip packaging solution for miniaturized massively parallel processing

The development and evaluation of a three-dimensional (3-D) interconnect and packaging technology for massively parallel processor (MPP) implementation is reported. Following reviews of specific modular massively parallel computer (MPC) accelerator and chip stacking technologies, the paper reports the progress of a collaborative research project to pioneer a novel MPP module. The design of a highly compact 3-D chip-stack, integrating five MPP chips in a single package, is described in detail. Problems encountered and their solutions are reported. Test results for prototype MPP chip-stacks provide proof-of-principle for the 3-D chip stacking approach. Allowing from 2:1 to 4:1 savings in the modular MPC implementation size, without significant increase in cost or loss of performance, the emerging MPP chip stacking technology offers a cost-effective solution for MPP miniaturization.