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The temporal stability of the clock signal has a profound effect on the performance of synchronous RSFQ digital systems. Short-term clock fluctuations, or clock jitter, can severely degrade system performance due to the hazard of timing constraint violations. Successful large-scale RSFQ digital systems will require highly stable multi-Gigahertz on-chip clock sources. To meet this need, methods for characterizing and measuring the short-term stability of such sources are required. In this paper we identify the relevant figure of merit to characterize and compare various clocks: the cycle-to-cycle standard deviation of the clock periods. We have developed experimental techniques for the measurement of this figure of merit and applied it to the characterization of an RSFQ ring oscillator. The experimental results are compared with results from a stochastic circuit simulator. We determined the value of jitter to be 1.52% at 10 GHz.
Date of Publication: June 1999