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Fabrication technology for high-density Josephson integrated circuits using mechanical polishing planarization

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4 Author(s)
H. Numata ; Fundamental Res. Labs., NEC Corp., Ibaraki, Japan ; S. Nagasawa ; M. Tanaka ; S. Tahara

A mechanical polishing planarization (MPP) process is developed with an endpoint detection method. MPP makes it possible to form self-aligned contacts on small junctions and to decrease parasitic inductance. It can also control the thickness of the insulation layers precisely. MPP was used to fabricate a 22 /spl mu/m/spl times/22 /spl mu/m vortex transitional memory cell and the cell operated correctly. The reliability of interlayer insulation was increased for 64-Kbit memory cell arrays fabricated using MPP. It is concluded that MPP is an effective technology for fabricating high-density Josephson circuits.

Published in:

IEEE Transactions on Applied Superconductivity  (Volume:9 ,  Issue: 2 )