Referenced Items are not available for this document.
The performance of analog circuits is sensitive to fabrication process and the layout of their physical masks. In this paper, a novel constraint-based methodology is proposed for the placement refinement of CMOS analog cell circuits. Constraint-based module generation and shaping process are also developed not only to optimize the layout shape, area but more importantly to guarantee the analog circuits performance. A hybrid-tree model is proposed to simultaneously represent the geometry, symmetry and parasitic constraints for the layout. Experimental results have shown the effectiveness of the proposed method
Published in:
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
(Volume:6
)
Date of Conference: Jul 1999
- Page(s):
- 408 - 411 vol.6
- Meeting Date :
- 30 May 1999-02 Jun 1999
- Print ISBN:
- 0-7803-5471-0
- INSPEC Accession Number:
- 6460057
- Conference Location :
- Orlando, FL
- Digital Object Identifier :
- 10.1109/ISCAS.1999.780181
- Product Type:
- Conference Publications
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