Cart (Loading....) | Create Account
Close category search window
 

The effects of predicated execution on architectures supporting dynamic speculation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Mantripragada, S. ; Silicon Graphics Inc., CA ; Nicolau, A.

Branch instructions pose a serious problem in achieving a good instruction level pamllelism (ILP) from a program. Modern microprocessors have attempted to alleviate this problem with the support of sophisticated branch prediction schemes. Dynamic speculation, as a hardware feature, is used to execute instructions out-of-order (OOO) guided by the outcomes of such prediction schemes. Previous branch outcomes are used to speculate an instruction before the branch is fully resolved. Studies have shown that inspite of such complex prediction schemes, there still exist many frequently executed branches which are hard to predict. Predicated execution has been proposed as an alternative technique by researchers to eliminate some of these hard to predict bmnches. Previous studies have analyzed the effects of applying predicated execution with branch prediction. Here, we study the effects of predicated execution on architectures supporting dynamic speculation. Branch classification, as a technique, is used to group branches with similar dynamic execution frequencies. The effects of different predication models on dynamic speculation are then studied for each of these branch classes. An in-depth analysis of useful and useless instructions as a result of applying these different models is also summarized.

Published in:

Innovative Architecture for Future Generation High-Performance Processors and Systems, 1998

Date of Conference:

24-24 Oct. 1998

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.