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The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as a multibit quantizer

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4 Author(s)
A. Iwata ; Fac. of Eng., Hiroshima Univ., Japan ; N. Sakimura ; M. Nagata ; T. Morie

This brief proposes a new- architecture for the oversampling delta-sigma analog-to-digital converter (ADC) utilizing a voltage controlled oscillator (VCO). The VCO, associated with a pulse counter, works as a high-speed quantizer. This VCO quantizer also has the function of first-order noise shaping because the phase of the output pulse is an integrated quantity of the input voltage. If the maximum VCO frequency (fvm) is designed in the range of (2bq-2)fos<fvm< (2bq-1) fos and a bq-bit counter is used, a multibit (bq-bit) quantizer can be realized, where fos is the oversampling frequency. The performance of the proposed converter is evaluated using a functional simulation. A 59-dB SNR at a 5-MHz bandwidth is obtained with fos=400 MHz, even in the case of a 1-bit quantizer. The multibit quantizer using a high frequency VCO significantly improves an SNR and signal bandwidth. This architecture is highly suitable for implementation with deep sub-μm CMOS devices, which can attain improved switching speeds and reduce power dissipation during low voltage operation. It provides wideband oversampling ADC for video and wireless signals and a low voltage system-on-a-chip solution for multimedia applications

Published in:

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing  (Volume:46 ,  Issue: 7 )