By Topic

A novel 6H-SiC power DMOSFET with implanted p-well spacer

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Vathulya, V.R. ; Sherman Fairchild Center for Solid State Studies, Lehigh Univ., Bethlehem, PA, USA ; Shang, H. ; White, M.H.

We utilize a lower thermal budget with an aluminum doped p-well to minimize the effect of "step bunching" and a new structural design with deep spacer implants to prevent the JFET "pinching" action at small p-well spacings (5 μm) in planar vertical double implanted MOSFET (DIMOS) devices fabricated on 6H-SiC. A specific ON-resistance of 42 m/spl Omega/-cm2 (further reducible by 35% through simple design modification), which represents a 100% reduction over devices which did not receive the spacer implants, is observed on the 2-μm channel devices. This novel scheme will allow increased packing densities for high power applications using the DIMOS structure in SiC.

Published in:

Electron Device Letters, IEEE  (Volume:20 ,  Issue: 7 )