By Topic

Modeling interconnection networks using a hardware description language

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Freytag, L.R. ; Dept. of Comput. Eng., Florida Atlantic Univ.,, Boca Raton, FL, USA

Using a hardware descriptive language, it is possible to develop simulation models for processor interconnection networks which take hardware considerations into account during simulation. Models were produced for nine interconnection networks, specialized first for a simple algorithm, then adapted for a more complex task. Simulations were conducted to ensure the correctness of the models, and the complexities involved in expanding the simple example into the more complex one were considered. In particular, simulation results obtained with the DABL (Daisy Behavioral Language) model are presented. The DABL models were capable of providing more insight into hardware-related issues than simulations conducted in conventional programming languages

Published in:

Databases, Parallel Architectures and Their Applications,. PARBASE-90, International Conference on

Date of Conference:

7-9 Mar 1990