By Topic

Uninterpreted modeling using the VHSIC hardware description language (VHDL)

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Hady, F.T. ; Supercomput. Res. Center, Bowie, MD, USA ; Aylor, J.H. ; williams, R.D. ; Waxman, R.

The authors discuss methodologies and tools that allow a system to be analyzed using Petri nets or queuing models. Models at this level contain tokens rather than values, and the function of blocks remains undefined. Such analysis is performed early in the design process to evaluate overall system performance. Different methodologies and tools are available to allow design analysis and verification at interpreted levels through hardware design language (HDL) descriptions. Tokens are replaced with specific values for the representation of signals. The methodology presented allows the designer to create uninterpreted models in an environment already capable of interpreted modeling, the VHSIC hardware description language (VHDL). Uninterpreted modeling in an HDL is the first step in the creation of a continuous single-path design environment.<>

Published in:

Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on

Date of Conference:

5-9 Nov. 1989