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Timed trace theoretic verification using partial order reduction

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2 Author(s)
T. Yoneda ; Dept. of Comput. Sci., Tokyo Inst. of Technol., Japan ; H. Ryu

In this paper, we have extended the trace theoretic verification method with partial order reduction so that it can properly handle timed circuits and timed specification. The partial order reduction algorithm is obtained from the timed version of the Stubborn set method. The experimental results with the STARI circuits show that the proposed method works very efficiently

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Advanced Research in Asynchronous Circuits and Systems, 1999. Proceedings., Fifth International Symposium on

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