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Accounting for various register allocation schemes during post-synthesis verification of RTL designs

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2 Author(s)
N. Mansouri ; Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA ; R. Vemuri

This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization schemes commonly found in high-level synthesis tools. Performing register optimization as part of synthesis process implies that the mapping between the specification variables and RTL registers is not bijective. We propose a formalization of dynamic variable-register mapping, and techniques based on symbolic analysis and higher-order logic theorem proving for verifying synthesized RTL designs. The proposed verification methodology has been successfully implemented using the PVS theorem prover.

Published in:

Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings

Date of Conference:

9-12 March 1999