Referenced Items are not available for this document.
This paper presents a technique for glitch power minimization in combinational circuits. The total number of glitches is reduced by replacing some existing gates with functionally equivalent ones (called F-gates) that can be "frozen" by asserting a control signal. A frozen gate cannot propagate glitches to its output. An important feature of the proposed method is that it can be applied in-place directly to layout-level descriptions; therefore, it guarantees very predictable results and minimizes the impact of the transformation on circuit size and speed.
Published in:
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings
Date of Conference: 9-12 March 1999
- Page(s):
- 163 - 167
- Meeting Date :
- 09 Mar 1999-12 Mar 1999
- Print ISBN:
- 0-7695-0078-1
- INSPEC Accession Number:
- 6375762
- Conference Location :
- Munich, Germany
- Digital Object Identifier :
- 10.1109/DATE.1999.761113
- Product Type:
- Conference Publications
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