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Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)

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The following topics were dealt with: embedded system design; verification of sequential circuits; architectural issues in low power design; design reuse repository and IP architecture; high level verification; system-level power optimization; reconfigurability; embedded core test approaches; combinational verification; gate level power estimation and optimization; Virtual Socket Interface Alliance; fault diagnosis techniques for analogue circuits; resource sharing in architectural synthesis; mixed signal characterization and test; system design methodologies; high level test synthesis; analogue circuit sizing and synthesis; high-level system simulation; VHDL-AMS and HDL interoperability; transistor level test; hardware synthesis from C/C++ models; chip package co-design; scaling towards nanometer technologies; functional verification; bit-level logic simulation; partial and boundary scan test; logic synthesis; defect modelling; physical design issues; reliability and symmetry; retiming; interconnects modelling; virtual components; RAM BIST; sequential circuit test generation

Published in:

Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings

Date of Conference:

9-12 March 1999