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A 5.3-GB/s embedded SDRAM core with slight-boost scheme

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12 Author(s)
Yamazaki, A. ; Mitsubishi Electr. Corp., Hyogo, Japan ; Yamagata, T. ; Hatakenaka, M. ; Miyanishi, A.
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This paper describes a slight-boost scheme to improve a transistor performance in system large-scale integrated circuits, which integrate logic circuits and 1-Tr/1-C DRAMs. In this scheme, an embedded SDRAM core has been developed for graphic and multimedia applications. Its maximum operating frequency is 166 MHz, with a peak data rate of 5.3 GB/s. As well, a fast row-address access time of 22 ns has been achieved. The SDRAM core has been fabricated by means of a 0.3-μm quad-polysilicon, triple metal, triple-well CMOS process. This SDRAM core has a block write function, enhanced by a multiselect block write scheme, and a synchronous direct memory-access test circuit has been implemented to reduce the number of test pads

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:34 ,  Issue: 5 )