Referenced Items are not available for this document.
A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 μm CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:34
,
Issue:
5
)
Date of Publication: May 1999
- Page(s):
- 599 - 606
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 6248057
- Digital Object Identifier :
- 10.1109/4.760369
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- May 1999
- Sponsored by :
- IEEE Solid-State Circuits Society
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