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Median biased Steiner tree heuristics in the rectilinear plane for low-power physical layout

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2 Author(s)
Jimenez, M.A. ; Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA ; Shanblatt, M.A.

Two heuristics are proposed for the rectilinear Steiner-minimum tree (SMT) problem arising when interconnecting multiple terminals in a layout with obstacles. Efficient algorithms are implemented to convert circuit layouts into graphs. A set of reduction techniques are implemented to remove unfeasible vertices. These techniques delete an average of over 90% of the m Steiner candidates in O(m2) time. The proposed SMT heuristics grow trees biased by the terminal distances of the n vertices in a graph in O(n2.log n) time. The results obtained highlight their suitability to be used as wire length estimators in a power optimizing placement tool

Published in:

Circuits and Systems, 1998. Proceedings. 1998 Midwest Symposium on

Date of Conference:

9-12 Aug 1998