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Locally-clocked dynamic logic

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3 Author(s)
G. Hoyer ; Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA ; Gin Yee ; C. Sechen

Locally-clocked (LC) dynamic logic is a circuit methodology which combines a localized clocking strategy with a robust dynamic gate design to provide a high throughput, low latency circuit solution. LC dynamic logic creates event-driven pipelines which outperform and avoid many of the problems associated with conventional clock-based pipeline techniques. LC dynamic logic was used to implement an 8×8 bit multiplier design that operates at 715 MHz in a 1.0 μm MOSIS process, which exceeds the highest multiplier frequency previously published

Published in:

Circuits and Systems, 1998. Proceedings. 1998 Midwest Symposium on

Date of Conference:

9-12 Aug 1998