Super CSP^TM: WLCSP solution for memory and system LSI

Wafer level CSP (WLCSP) has been paid great attention due to its miniature size. It is a real chip size package from the package perspective. It is also a known good encapsulated die (KGED) from the die perspective. This means that the boundary between package and bare die becomes indistinct. It sometimes referred to as a `packageless' package. It is no longer meaningless to enquire whether CSP or bare die should be used since WLCSP is emerging. WLCSP is shaped by wafer level packaging (WLP) and wafer level testing (WLT). At this time, eight WLCSPs are proposed using different kinds of WLP. Three WLT are also proposed, including the authors' own technology. We developed the Super CSP^TM using a unique WLP with five major processes: re-routing, metal-post forming, compression moulding, solder ball placing and dicing. This package allows a system designer to layout a motherboard at the smallest area possible. It also allows an assembly engineer to mount on a motherboard and replace from the motherboard similar to conventional CSPs, and allows a test engineer to test and burn-in much more easily than with known good die (KGD). We confirmed excellent electrical performance, package reliability, mountability, and second level packaging reliability