Referenced Items are not available for this document.
A method of reducing aliasing in built-in self-test of VLSI circuits is proposed. The method is based on the use of transition count testing. A new formulation of the problem is given in terms of finding a test generator as opposed to solving the problem at the data compaction end. An algorithm is proposed which can be used to find a counter-based test pattern generator. This test generator tests a circuit exhaustively or pseudo-exhaustively so that the aliasing is reduced substantially provided the data compactor used is a transition counter. Experimental results are presented to substantiate these claims
Published in:
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
(Volume:10
,
Issue:
4
)
Date of Publication: Apr 1991
- Page(s):
- 548 - 553
- ISSN :
- 0278-0070
- INSPEC Accession Number:
- 3909965
- Digital Object Identifier :
- 10.1109/43.75640
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Apr 1991
- Sponsored by :
- IEEE Council on Electronic Design Automation
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