VSPEC constraints modeling and evaluation

Performance constraints play a key role in VLSI design. Performance constraints evaluation help in discovering requirements specification errors at an early stage in the design process when they are easy to fix. VSPEC is a requirements specification language for digital systems that contains a standard method for describing constraints. The paper presents a method of evaluating and verifying these constraints. Performance Description Language (PDL) is used for evaluation. The system is implemented within the ORBIT design environment.