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We have developed a new approach to behavioral synthesis for testability. Utilizing a VHDL transformation environment, we have distilled design rules for testable VHDL generation. Design rules can be linked to specific design for test techniques, allowing simplified exploration of BIST, partial scan, and other test approaches. The result is a design methodology which is simple to use, improves testability, and decreases time to market.
Signals, Systems & Computers, 1998. Conference Record of the Thirty-Second Asilomar Conference on (Volume:2 )
Date of Conference: 1-4 Nov. 1998