Referenced Items are not available for this document.
We have developed a new approach to behavioral synthesis for testability. Utilizing a VHDL transformation environment, we have distilled design rules for testable VHDL generation. Design rules can be linked to specific design for test techniques, allowing simplified exploration of BIST, partial scan, and other test approaches. The result is a design methodology which is simple to use, improves testability, and decreases time to market.
Published in:
Signals, Systems & Computers, 1998. Conference Record of the Thirty-Second Asilomar Conference on
(Volume:2
)
Date of Conference: 1-4 Nov. 1998
- Page(s):
- 1033 - 1037 vol.2
- Meeting Date :
- 01 Nov 1998-04 Nov 1998
- ISSN :
- 1058-6393
- Print ISBN:
- 0-7803-5148-7
- INSPEC Accession Number:
- 6324981
- Conference Location :
- Pacific Grove, CA, USA
- Digital Object Identifier :
- 10.1109/ACSSC.1998.751419
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