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Advancements in VLSI technology allow for the digitization of communication systems and the utilization of more sophisticated signal processing algorithms, such as turbo codes for stronger forward error correction (FEC) processing. However, commiserate improvements must also occur in front-end processing for signal acquisition. A new architecture that merges the functionality of front-end and back-end signal processing for more VLSI efficient hardware in low SNR (LSNR) communications environments offering the potential to reduce the overall complexity and cost of the implementation is presented. Simulations show that this architecture is comparable in performance with current implementations.