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This paper describes a high level design for camera motion estimation and details an efficient implementation of a feature point detection technique known as the "Kanade-Lucas-Tomasi" (KLT) algorithm. After making several novel approximations, an efficient, high-performance field-programmable gate-array (FPGA) design that does not sacrifice detection performance is presented. The high level design couples the FPGA with a conventional digital signal processor to enable full video rate throughput. Results of the FPGA-based feature point detection as well as its application to camera motion estimation are shown.