By Topic

Application of STD to latch-power estimation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Zyuban, V. ; Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA ; Kogge, P.

In this paper, we use the recently developed static transition diagram technique to derive analytical formulas expressing latch power in terms of true and spurious switching activities at the data input. These formulas are verified through analog simulation and applied to a number of commonly used latch designs. The derived model will allow designers to substitute parameters of true and spurious switching activities into analytical formulas for quickly obtaining accurate latch power and then select latches which have the best power-dissipation characteristics for those parameter values.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:7 ,  Issue: 1 )