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Design and optimization of dual-threshold circuits for low-voltage low-power applications

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6 Author(s)
L. Wei ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Z. Chen ; K. Roy ; M. C. Johnson
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Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general leakage current model which has been verified by HSPICE simulations is used to estimate leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the leakage power can be reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively.

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:7 ,  Issue: 1 )