Referenced Items are not available for this document.
In slotted, dual-bus systems, M stations are connected to two unidirectional buses in a linear order and transmissions use slots passing through the stations. If a slot is used by a station i to transmit to a station j, j>i, then the slot can be reused by a station k, k⩾j. We show that the necessary and sufficient length of addresses for full slot reuse is M-2 bits for w=0 and [(M-1)/2w-1 ]+w-2 bits for w⩾1 and M>1+2w, where w is the bit delay at every station
Published in:
Information Theory, IEEE Transactions on
(Volume:45
,
Issue:
1
)
Date of Publication: Jan 1999
- Page(s):
- 356 - 365
- ISSN :
- 0018-9448
- INSPEC Accession Number:
- 6192095
- Digital Object Identifier :
- 10.1109/18.746844
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Jan 1999
- Sponsored by :
- IEEE Information Theory Society
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