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Diagnostic test pattern generation for analog circuits using hierarchical models

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2 Author(s)
Chakrabarti, S. ; Georgia Inst. of Technol., Atlanta, GA, USA ; Chatterjee, A.

In this paper we propose a novel fault-based transient test generation methodology for locating faults in hierarchical nonlinear analog circuits. A heuristic optimization algorithm generates test stimuli that can distinguish fault-effects based on voltage measurements at observable circuit nodes. hierarchical fault dictionaries are generated for the purpose of fault location. The cost of simulation during dictionary construction is significantly reduced as the proposed method uses hierarchical behavioral modeling of circuits and fault dropping techniques. The proposed algorithms can also be used to generate tests for fault detection. A complete diagnostic test generation system has been implemented and tested successfully

Published in:

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Date of Conference:

7-10 Jan 1999