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A test generator for segment delay faults

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3 Author(s)
K. Heragu ; DSPS R&D Center, Texas Instrum. Inc., Dallas, TX, USA ; J. H. Patel ; V. D. Agrawal

We propose a simulation-based technique that uses a genetic algorithm (GA) to generate tests for delay faults on segments of any given length. At every line, we assume that an upper bound on the number of testable segment faults that originate there is known. Such a bound is efficiently computed by an implication-based technique. The fitness function for the GA is derived from an objective function that favors vectors which might detect a large number of faults. This is accomplished by a simulator used as a base engine, by dynamically identifying a line m with the highest upper bound for the number of segments on which faults can and are yet to be tested, and by ranking vectors according to their ability to target the simultaneous objectives of invoking a transition on m and maximizing the number of signals that propagate robustly in the fanout cone of m. Rather than limiting the number of generations of evolution in the GA, we obtain improved results by using the diversity of the individuals in a population as a stopping criterion. Results indicate that for small segment lengths, reasonable robust segment delay test coverages can be obtained for most benchmark circuits. Also, the tests generated using the segment delay fault model detect a large number of transition and path delay faults. For example in the benchmark circuit c3540, tests generated for faults on segments of length 5 had a transition fault coverage of 96.1% and were able to detect 9,246 path faults

Published in:

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Date of Conference:

7-10 Jan 1999