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The retiming of single-phase clocked circuits containing level-sensitive latches

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3 Author(s)
Saxena, P. ; Strategic CAD Labs., Intel Corp., Hillsboro, OR, USA ; Peichen Pan ; Liu, C.L.

Previous approaches to the retiming of latch-based circuits have used the different phases of the clock to prevent race conditions. However, such an approach is not applicable to single-phase clocked circuits. Consequently there is no practical formulation that retimes single-phase clocked circuits containing latches optimally. We present a novel ILP formulation for the retiming of such circuits, along with efficient algorithms to generate its constraint set. This formulation can be used to optimize any criterion whose quality depends on the latch positions and that can be expressed as a linear objective function. As examples, we discuss the optimization of the clock period and the latch count. For the latter we describe a graph transformation to linearize the max-based objective function. Our experiments demonstrate that our formulation is efficient and generates ILPs that are easy to solve

Published in:

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Date of Conference:

7-10 Jan 1999

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