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Incorporating process induced effects into RC extraction

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5 Author(s)
Li-Fu Chang ; Frequency Technol. Inc., San Jose, CA, USA ; A. Dubey ; Keh-Jeng Chang ; R. Mathews
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With the advent of deep-submicron technologies, more and more process-induced effects become first-order influences to the performance of VLSI chips. In this paper we will describe a set of wafer-level electrical measurement methods which we have used to measure process-induced effects for several deep-submicron technologies. Seven important interconnect performance parameters have been identified as a minimum set of parameters needed to accurately accommodate the effects and predict the resistance and capacitance of the state-of-the-art interconnect systems. Therefore, interconnect parasitic estimation, or interchangeably in this paper, RC extraction, has to be improved to incorporate those parameters. It is also essential that process/TCAD describes those parameters in a format that allows more accurate parasitic estimation

Published in:

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Date of Conference:

7-10 Jan 1999