Referenced Items are not available for this document.
An analytical method is described for determining the random pattern testability of faults in combinational logic feeding the address inputs of embedded memories. Difference information from replicated copies of embedding logic is used to determine the probability of detecting any fault in the upstream of either a read or write port address decoder. The method can be used with minor extensions to existing detection probability tools such as the cutting algorithm
Published in:
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
(Volume:17
,
Issue:
12
)
Date of Publication: Dec 1998
- Page(s):
- 1310 - 1318
- ISSN :
- 0278-0070
- INSPEC Accession Number:
- 6136602
- Digital Object Identifier :
- 10.1109/43.736570
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Dec 1998
- Sponsored by :
- IEEE Council on Electronic Design Automation
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