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Towards real time fault identification in plasma etching using neural networks

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2 Author(s)
Zhang, B. ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; May, G.S.

As the IC industry moves further into sub-μm fabrication technology, optimal fabrication equipment utilization is essential. Timely and accurate equipment malfunction identification can be key to success. It is also desirable to predict malfunctions well in advance of actual occurrence. In this paper, we use neural nets to model time series data extracted from a three-step plasma etch process for defining active areas in a CMOS ASIC. The data consists of real-time measurements from the three-step etch process for 140,000 silicon wafers collected over a six-month period from a Drytek plasma etcher. Two types of anomalies were present in this data: (1) constant or slowly advancing time (indicating the presence of a machine fault); and (2) missing steps (indicating something unexpected happened during the etch). Data preprocessing is carried out to eliminate any data acquisition errors in the original data and to separate the total time sequence into three sub-sequences (one per etch step). A pattern recognition technique is used to determine the process step number for each record. The classification results and the prediction error demonstrate accurate determination of the etch step number from the chamber state. Dynamic neural net models are then constructed for each step. We initially focus on modeling the time series associated with chamber pressure. The time series of pressure data is modeled as a function of its previous values and the current time. We use this approach to construct time series models of the etching system pressure variations using only the initial condition and the time value as inputs

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 1998. 1998 IEEE/SEMI

Date of Conference:

23-25 Sep 1998