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Rate optimal VLSI design from data flow graph

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2 Author(s)
Moonwook Oh ; Dept. of Comput. Eng., Seoul Nat. Univ., South Korea ; Soonhoi Ha

This paper considers the rate optimal VLSI design of a recursive data flow graph (DFG). Previous research on rate optimal scheduling is not directly applicable to VLSI design. We propose a technique that inserts buffer registers to allow overlapped rate optimal implementation of VLSI. We illustrate that nonoverlapped schedules can be implemented by a simpler control path but with a larger unfolding factor, if it exists, than overlapped schedules.

Published in:

Design Automation Conference, 1998. Proceedings

Date of Conference:

19-19 June 1998

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