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Design methodology used in a single-chip CMOS 900 MHz spread-spectrum wireless transceiver

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3 Author(s)
J. Rael ; Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA ; A. Rofougaran ; A. Abidi

Most CAD tools cater to digital IC design and enable an entire system to be simulated at a behavioral level. When the designer is satisfied with a particular architecture, a netlist can be automatically synthesized and laid out. This is in sharp contrast to tools for analog IC design; no single platform exists for the automated design of an RF transceiver. This paper describes the design flow and CAD tools used in the design, simulation, and layout of a single-chip 900 MHz CMOS wireless transceiver. Large sections of this chip were simulated and laid-out using tools meant for digital circuit design. These tools did not have features to assist in analog layout and simulation, but allowed us to take advantage of the extensive silicon generators developed by our digital design group. We were forced to improvise when the existing tools could not meet our needs, or when no tool existed for the task. With this design flow, we produced a chip with measured results on first silicon very close to simulation.

Published in:

Design Automation Conference, 1998. Proceedings

Date of Conference:

15-19 June 1998