Referenced Items are not available for this document.
In this paper, we propose a new phase locked loop (PLL) frequency synthesizer utilizing the multiprogrammable divider which can attain a higher speed lock-up time by increasing the loop gain. The effectiveness of the PLL frequency synthesizer with the multiprogrammable divider are shown by theoretical considerations and experimental results
Published in:
Consumer Electronics, IEEE Transactions on
(Volume:44
,
Issue:
3
)
Date of Publication: Aug 1998
- Page(s):
- 827 - 832
- ISSN :
- 0098-3063
- INSPEC Accession Number:
- 6043932
- Digital Object Identifier :
- 10.1109/30.713201
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Aug 1998
- Sponsored by :
- IEEE Consumer Electronics Society
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
