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VLSI architecture of signal processing chip set for 42-inch DC PDP HDTV receiver

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5 Author(s)
Kokubun, Hideki ; Japan Broadcasting Corp., Tokyo, Japan ; Takano, Y. ; Yamamoto, T. ; Ishii, K.
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A signal processing chip set for 42-inch DC PDP HDTV receivers has been developed. Four kinds of signal processing LSIs are fabricated with a semi-custom LSI design and 0.35 μm triple-metal CMOS technology. This paper describes the architecture of the LSI chip set and new circuit configurations to improve the picture quality. The chip set has enabled a practical PDP HDTV receiver to be fabricated

Published in:
Consumer Electronics, IEEE Transactions on  (Volume:44 ,  Issue: 3 )

Date of Publication: Aug 1998

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