Referenced Items are not available for this document.
This paper describes the VLSI implementation with a two-dimensional (2-D) data-reuse architecture for a full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed VLSI architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates
Published in:
Consumer Electronics, IEEE Transactions on
(Volume:44
,
Issue:
3
)
Date of Publication: Aug 1998
- Page(s):
- 623 - 629
- ISSN :
- 0098-3063
- INSPEC Accession Number:
- 6043910
- Digital Object Identifier :
- 10.1109/30.713173
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Aug 1998
- Sponsored by :
- IEEE Consumer Electronics Society
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