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A methodology for task based partitioning and scheduling of dynamically reconfigurable systems

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3 Author(s)
P. Merino ; Dept. de Ingenieria Electron., Univ. Politecnica de Madrid, Spain ; M. Jacome ; J. C. Lopez

Taking maximum advantage of dynamic reconfiguration in the implementation of digital systems poses a number of challenging research problems. Specifically, techniques are needed to partition the system behavioral description into segments of computation (or “scheduling units”), and to define a reconfiguration schedule with respect to those units, so as to maximize the performance of the dynamically reconfigurable system, subject to the area constraints of the FPGA. We propose a methodology to: (1) perform a coarse-grained partitioning of the system behavioral description into a set of tasks, (2) determine which sub-set of tasks is to remain resident in the FPGA, and which sub-set is to be non resident, (3) generate a reconfiguration schedule for the non-resident tasks by specifying when such tasks should be loaded on to and erased from the FPGA

Published in:

FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on

Date of Conference:

15-17 Apr 1998